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Write a program in verilog to implement sequence detector 0110/10101

AIM: Write a program in verilog to implement sequence detector(0110/10101)
LEARNING OBJECTIVE:-To make the students familiar with concept of FSM and
how to implement different sequences using FSM
PROCEDURE:
1. Open a new project from the drop down menu by clicking in FILE given on the
top left of the screen.
2. Create a new project and name it.
3. Click on next to enter the device properties.
4. Select the appropriate properties according to the hardware to be used.
5. Click on the next button to enter the new source.
6. Here select the Verilog MODULE and give the file name.
7. Click on next button and enter the entity name.
8. Select the define module.
9. Select the ports as input and output and name them.
10. Click on next and then to on finish.
11. Write the code for the project under the library entity.
12. Save the program.
13. Select the behavioral simulation option from the three modeling options.
14. Now select the syntax check.
15. If the syntax check comes out to be correct, then precede further, otherwise check
errors.
16. Now select simulation option and select the test bench option.
17. Initialize the clock and other properties from the window that appears on the
screen.
18. Give the clock pulse to one of the inputs and save the program.
19. Click on simulate to get the output.

SEQUENCE DETECTOR 0110 MOORE


module seq_dect_0110 (clk,data_in,reset,data_out);
input clk, data_in, reset;
output reg data_out;
reg [2:0]pr_state,nx_state;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
always @ (posedge clk or posedge reset) begin
if (reset)
pr_state <= S0;
else
pr_state <= nx_state;
end
always @ (pr_state or data_in) begin
case (pr_state)
S0:
begin
data_out <= 0;
if (data_in ==1)
nx_state <= S0;
else
nx_state <= S1;
end
S1:
begin
data_out <= 0;
if (data_in==1)
nx_state <= S2;
else
nx_state <= S1;
end
S2:
begin
data_out <= 0;
45
if (data_in ==1)
nx_state <= S3;
else
nx_state <= S1;
end
S3:
begin
data_out <= 0;
if (data_in==1)
nx_state <= S0;
else
nx_state <= S4;
end
S4:
begin
data_out <= 1;
if (data_in)
nx_state <= S2;
else
nx_state <= S1;
end
endcase
end
endmodule


SEQUENCE DETECTOR 10101 MOORE


module seq_dect_10101(clk,data_in,reset,data_out);
input clk, data_in, reset;
output reg data_out;
reg [2:0]pr_state,nx_state;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5;
always @ (posedge clk or posedge reset) begin
if (reset)
pr_state <= S0;
else
pr_state <= nx_state;
end
always @ (pr_state or data_in) begin
ase (pr_state)
S0:
begin
data_out <= 0;
if (data_in ==1)
nx_state <= S1;
else
nx_state <= S0;
end
S1:
begin
data_out <= 0;
if (data_in==1)
nx_state <= S1;
else
nx_state <= S2;
end
S2:
begin
data_out <= 0;
if (data_in ==1)
nx_state <= S3;
else
nx_state <= S0;
end
S3:
begin
data_out <= 0;
if (data_in==1)
nx_state <= S1;
47
else
nx_state <= S4;
end
S4:
begin
data_out <= 0;
if (data_in)
nx_state <= S5;
else
nx_state <= S0;
end
S5:
begin
data_out <= 1;
if (data_in)
nx_state <= S1;
else
nx_state <= S2;
end
endcase
end
endmodule

 

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